Is a smaller production process always better? Intel offers a 10nm SuperFin differently


This article is part of the Technology Insight series, funded by Intel.

When it comes to manufacturing technology, we teach that smaller transistors are better. They switch faster and use less energy. They take up less space, freeing up more cores, more cache, and ultimately better performance. When foundries can accommodate more foundries on silicon wafers of the same size, costs are reduced. Not surprisingly, the world of technology anticipates that every process shrinks while holding your breath.

But not all nodes are created equal. Back in 2017 Mark Mark Bohr, former director of Intel’s process architecture and integration, said The 14nm company’s process had about a three-year advantage over the competitive 10nm technology with a similar density. In this case, density refers to the number of transistors packed per unit area (usually square millimeters). Interestingly, it also showed that improved versions of Intel’s 14nm node would actually surpass the first 10nm effort, albeit with higher levels of active power consumption.

Today, the improved 10nm transistors play a key role in helping Intel’s new Tiger Lake mobile platform achieve a higher clock speed than the previous-generation Ice Lake design. Transistors are at the same time faster and more efficient than any previous process competing with competitors ’7 nm technology. How is such a thing possible? Intel says the focus is on manufacturing innovation, in addition to the scale of traditional features such as new materials and device architecture. The resulting node at 10 nm is called “SuperFin” by Intel.

“The combined power of these innovations allows us to increase dramatic CPU performance, making it the biggest single-node improvement in Intel’s history,” says Dr. Ruth Brain, an Intel fellow in the technology and manufacturing team. Let’s take a closer look at the technologies that transmit the 10 nm process with what Dr. Brain, almost equivalent to the overall node transition performance.

Key issues

  • 10nm SuperFin Node is a long-awaited improvement on Intel’s first 10nm manufacturing process
  • Intel has implemented a number of innovations, in addition to smaller transistor features, to make a big difference
  • The planned 10 nm enhanced SuperFin process will be adapted for data center processors and GPUs

Performance and power is not just a node name

Once upon a time, nodes were specified according to the minimum size of the element – usually the length of the gate of the transistor or the distance that the electrons travel from the source of the transistor to the leak. This changed gradually as other parts of the transistor decreased and the length of the gate stopped changing so aggressively.

Back in 2017, we knew it would take a few node upgrades for Intel’s 10nm technology to go beyond a mature 14nm process.

Above: Back in 2017 We knew that for 10 percent. Intel technology to overcome the mature 14 nm process, will require multi-node improvements.

Today, node names largely reflect the progress of generations. They do not reflect the length of the gate; the pitch, width, or height of the fins of modern field effect transistors (FETs); or even the density of the transistor. Therefore, it is difficult to figure out marketing and compare competing process technologies by their names.

As Intel struggled to bring 10nm into production, the company now has to withstand the contrasts between its 10nm transistors and 7nm nodes from TSMC and Samsung. Fortunately for Intel, the 10 nm node maintains its position, although the name suggests otherwise. The large investment in the 10nm magnification made it easier for Intel ~ 2.7x density improvement over 14nm, packs more than 100 million transistors per square millimeter of matrix area.

“The aggressive scale has been enabled by innovations that have moved beyond the transistor device to metal connectors and ultimately at the cellular level,” Brain said at a recent Intel Architecture Day 2020 event.

Long road up to 10nm

One such innovation is self-harmonized quadricycle modeling, a process used to overcome the limits of lithographic resolution and create very dense interconnections. The Intel 10nm node is the first to use a self-adhesive quadrangular pattern on the lowest metal layers to connect the step scale from 52nm to 14nm fabrication to 36nm to bring the wires connecting the transistors closer together.

The same metal layers also use local cobalt joints for the first time, reducing the effects of electrical migration and halving the resistance compared to copper in the narrowest joining steps.

Intel’s 10 nm process also includes contact via active gate (COAG) technology. According to the Kaisad Ministry, Intel’s director of logic technology development, moving contacts from the traditional position near the transistor to the right above it improves the scale of the area by 10%.

Contact over gate technology is one of Intel's 10 nm process features that helps improve area scalability by about 10%.

Top: Contact over gate technology is one of Intel’s 10nm process features that helps improve area scalability by about 10%.

A further density scale at 10 nm is achieved by halving the number of gaskets or manikin gates between cells. At 14 nm, Intel used one mannequin gate at each end of its cell. With two windows next to each other, it looked like a pair of adjacent mannequin gates. The windows can now be shared by a single gate, providing an additional ~ 20% area scaling.

With the improvement of Intel’s 10 nm process technology, we delayed production volumes more than the company would have liked. However, they eventually laid the groundwork for the improvements found in the 10 nm SuperFin. “The era of massive performance is simply behind us due to the simply declining functions of the transistors,” Brain said. Improvements to the process package now promise great momentum.

10 nm SuperFin = SuperMIM + redefined FinFET

Many years after the 14nm intranode enhancements were removed, Intel is a little more creative in its nomenclature. 10 nm SuperFin is obtained again I knew itr MIM (metal-insulator-metal) capacitor design and what the company calls a redefined The endFET.

Some of the 10nm SuperFin enhancements are for Intel transistor design improvements.

Above: Some of the 10nm SuperFin enhancements focus on Intel transistor design improvements.

“Inside the transistor, we improved the epitaxial growth of crystalline structures at source and leakage by increasing the voltage and reducing the resistance,” Brain said. As a result, more current may flow through the channel. Improvements to FinFET’s source and leakage architecture further improve channel mobility and allow charge carriers such as electrons to move faster. In addition, a larger gate pitch creates the possibility of a higher drive current to serve performance-dependent chip functions. Together, these transistor-level enhancements allow the 10nm SuperFin to achieve higher clock speeds at any voltage compared to the original Intel 10nm processor.

The 10nm SuperFin process uses thinner barrier materials that reduce vertical access access (re) resistance by 30%. If you are interested in difficult reading, view this presentation written by dr. Paul Besser of the Northern California Division of AVS back in 2017. But in short, he stresses that resistance is a growing concern as the bonding step decreases (hence the transition of certain metal layers to cobalt). The use of new 10nm SuperFin barrier materials further solves the problem of resistance and improves joint efficiency.

Intel says the Super MIM cap increases capacity by up to 5 times.  The result is a voltage reduction that improves performance.

Above: The Super MIM cap increases capacity by up to 5 times, according to Intel. The result is a voltage reduction that improves performance.

Even more significant is the Super MIM capacitor, which Intel says increases capacity by 5 times the industry standard. “This innovation is enabled by a new class of Hi-K dielectric materials stacked in ultra-thin, just a few angstroms thick layers to form a repetitive super-lattice structure,” Intel’s brain said during the presentation. The increase in capacity makes it possible to reduce the voltage, which again benefits.

Put rubber on the road in Tiger Lake

With just one intranode enhancement, the 10nm SuperFin delivers gains almost equal to the entire node transition, the company says. If that proves to be the case, this year’s Tiger Lake on-chip (SoC) system, built with 10nm SuperFin, should be huge.

Intel says it has optimized Tiger Lake for the 10nm SuperFin process. Thus, the SoC quad-core Willow Cove processor can hit high frequencies in the same power packs as its predecessor. This fact alone is expected to improve performance more than times.

Virtually 10nm SuperFin allows the future Willow Cove core to operate at a higher clock frequency of any fixed voltage or to reduce the voltage at a certain frequency.

Above: 10nm SuperFin allows the future Willow Cove core to operate at a higher clock frequency of any fixed voltage or to reduce the voltage at a certain frequency.

SuperFin should also help maintain the higher clock speed of Intel’s Xe graphics architecture. Given that Tiger Lake also boasts 50% more execution units than the previous generation Ice Lake SoC, it is a clear conclusion that 3D workloads will increase significantly.

A promising future beyond 10 nm

The first products based on Intel’s 10 nm processor were not as powerful as those developed using mature 14 nm node enhancements. This changes with 10 nm SuperFin. Clearly, the company’s data center teams saw what was going on and asked for additional features that would benefit their products as well.

Although Intel Architecture Day 2020 Speaking about information about the 10 nm enhanced SuperFin technology, she said the improvements will focus on better interconnection performance to transfer a lot of data across chips. Future Xeon and Xe-HP processors can be said to use Enhanced SuperFin to leverage Intel’s scalar and vector architectures in a better-built history.

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