Intel relies heavily on advanced chip packaging technology to fight for high-end computing


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This article is part of the Technology Insight series, funded by Intel.

We tend to focus on the latest and greatest technological assemblies as they are used to produce the densest, fastest and most energy efficient processors. However, as we were reminded at the recent Intel Architecture Day 2020, heterogeneous systems require a variety of transistor designs.

“No transistor is optimal at all design points,” said chief architect Raja Koduri. “The transistor we need for a desktop desktop to reach ultra-high frequencies is very different from the transistor we need for high-performance integrated GPUs.”

Here’s the problem: assembling the processing cores, fixed-action accelerators, graphics resources, and input / output, and then engraving them all on a monolithic meter at 10 nm, makes production very, very, and complex. But the alternative – to break them up and link the works – presents its challenges. Packaging innovations overcome these barriers by improving the interface between dense circuits and the boards in them.

The smart package is the mixing and tuning of the right transistors for each program to speed up performance time and maximize performance.

Above: Advanced packaging is the mixing and tuning of the right transistors for each program to speed up performance time and maximize performance.

As early as 2018. Intel has come up with a plan for smaller devices to work together without losing speed. “We said we need to develop technology to combine chips and chips into a package that matches the performance, energy efficiency and cost of a monolithic SoC.” Koduri continued. “We also said we need a high-density interconnection plan that would enable high bandwidth at low power.”

In an industry eager to name winners and losers based on process technology, an innovative approach to packaging will force multipliers in the fight for top computing. Let’s take a look at the current Intel Packaging Booklet along with the announcements revealed during the recent Architecture Day 2020.

KEY ISSUES:

  • The Embedded Multi-die Interconnect Bridge (EMIB) facilitates die-and-die connections using small silicon bridges embedded in the base of the package.
  • Advanced Interface Bus (AIB) is an open source interconnection standard for creating high-speed / low-power connections between schemas
  • Foveros packs packaging into the third dimension with stacked punches. The first Fovera-based product will be designed for the space between laptops and smartphones.
  • Co-EMIB and Omni-Directional Interface promise to expand current Intel packaging technology and facilitate flexibility.

Overcoming monolithic growing pains using EMIB

Until recently, if you wanted heterogeneous dies to be in one package to ensure maximum performance, you placed those dies on a piece of silicon called an interposer and routed the wires through the interposer for communication. Through the silicon coils (TSV) – the electrical connections – are transmitted through the device to the base that formed the base of the package.

The industry calls it 2.5D packaging. TSMC used it in the production of the NVIDIA Tesla P100 accelerator back in 2016. A year ago, AMD combined a huge GPU and 4 GB of high-speed memory (HBM) on a silicon interposition to create the Radeon R9 Fury X. Clearly, technology works. But this adds a characteristic layer of complexity, reducing yields and adding high costs.

Intel’s Embedded Multi-Link Bridge (EMIB) aims to ease the limitations of 2.5D packaging by launching a bracket in favor of small silicon bridges embedded in the substrate layer. The bridges are loaded with microcorners that facilitate connections.

“The current generation of EMIB is offering a 55-micron micro-bump step with guidelines to reach 36 microns,” said Ramune Nagisetty, Intel’s director of process and product integration. Compare this to the 100 micron stroke step of a typical organic package. EMIB allows a much higher impact density to be achieved.

Small silicon bridges are also much cheaper than intermediates. While the Tesla P100 and Radeon R9 Fury X were expensive flagships, one of Intel’s first products with embedded bridges was the Kaby Lake G, a mobile platform that combined an eighth-generation Core processor and an AMD Radeon RX Vega M ”schedule. Kaby Lake G-based laptops were by no means cheap. However, they have shown that EMIB is able to die heterogeneously in a single package, consolidating valuable board space, increasing productivity and reducing costs compared to individual components.

In this example, EMIB creates a high-density connection between the Stratix 10 FPGA and two transceivers.

Above: In this example, EMIB creates a high-density connection between the Stratix 10 FPGA and two transceivers.

Intel’s Stratix 10 FPGA also uses EMIB to combine three different foundries made using six different technology assemblies, I / O chips and HBM into one package. By disconnecting transceivers, I / O, and memory from the base fabric, Intel can pick and choose the design of each punch transistor. Adding support CXL, faster transceivers or Ethernet is as easy as replacing modular tiles connected via EMIB.

Standardized integrated die-to-die integration with Advanced Interface Bus

In order to mix and match chips, reusable IP blocks need to know how to talk to each other through a standardized interface. The Stratix 10 FPGA, Intel’s built-in bridges between the base fabric and each tile have an Advanced Interface Bus (AIB).

AIB has been designed so that the modular integration of the package is the same as PCI Express facilitating integration on the motherboard. But although PCIe drives at very high speeds over multiple wires, AIB utilizes EMIB density to create a wide parallel interface operating at a lower tactical frequency, simplifying transmission and reception schemes while still achieving very low latency.

The reusable IP blocks in the package can be connected via silicon bridges or gaskets using the Advanced Interface Bus to transfer data over a wide parallel connection.

Above: The reusable IP blocks in the package can be connected via silicon bridges or gaskets using the Advanced Interface Bus to transfer data over a wide parallel connection.

The first generation of AIB offers 2 Gb / s wired signaling, allowing Intel to see heterogeneous integration with monolithic SoC-like performance. The second-generation version, which is expected to be available in 2021, supports up to 6.4 Gb / s per wire, even 36 micron shocks, lower bit rate and backward compatibility with existing AIB deployments.

It is worth mentioning that AIB packs agnostic. While Intel connects its tiles using EMIB, TSMC Chip-on-Wafer-on-Substrate (CoWoS) technology could also transport AIB.

Earlier this year, Intel became a member of the Common Hardware, Interface, Processor, and Systems (CHIPS) Alliance, organized by the Linux Foundation, to contribute to the AIB license as an open source standard. The idea, of course, was to encourage the uptake of industry and to facilitate the library of AIB-equipped students.

“We currently have 10 AIB-based tiles from several suppliers that are manufactured or turned on,” says Nagisetty, an Intel company. “There will be another 10 tiles from ecosystem partners in the near future, including start-ups and university research groups.”

Foveros increase density in the third dimension

Breaking down SoCs into reusable IP blocks and integrating them horizontally into high-density bridges is one of the ways Intel plans to leverage production efficiencies and continue productivity. The next step forward, according to the company’s packaging technology plan, involves stacking punches on top of each other, face to face, using small microalgae. This three-dimensional method, which Intel calls Foveros, closes the distance between the dies, using less energy to transfer data. Although Intel’s EMIB technology is rated at around 0.50 pJ / bit, Foveros reduces it to 0.15 pJ / bit.

The first Lakefield product, based on the accumulation of Foveros 3D punches, includes a main punch (22FFL) after computational punch (10 nm), all of which are complemented by “pack-on-pack” memory.

Above: Lakefield, the first product based on Foveros 3D punch accumulation, consists of a base punch (22FFL) after computational punching (10 nm), all complemented by a memory pack.

Like EMIB, Foveros allows Intel to choose the best process technology for each layer of its stack. The first installation of Foveros, codenamed Lakefield, turns the core, memory management and graphics into a 10 nm duct. That chip is on the main die, which includes the functions you would normally find in a platform controller hub (audio, memory, PCIe, etc.) produced in a 14 nm low-power process. Micro shocks between the two pipe power supplies and communications through the TSV are basically dying. Intel then takes over one of its partners with LPDDR4X memory.

The full Lakefield package is only 12x12x1mm, allowing for new-class devices between laptops and smartphones. However, we do not expect Foveros to serve only low-power applications. 2019 Wilfred Gomes, an Intel fellow, at the HotChips Q&A session predicted the spread of future technology. “… the way we built Foveros, we think it will cover the full range of computing, from low-end devices to high-end devices,” he said.

Scale gives us another variable to consider

In the packaging plan set out during Intel Architecture Day 2020, each technology was represented in terms of connection density (number of microbumps per square millimeter) and energy efficiency (pJ of energy consumed per bit of data transmitted). In addition to Fovera, Intel uses a hybrid plate-to-plate connection to push both metrics even further. It is expected to achieve more than 10,000 strokes / mm² and less than 0.05 pJ / bit.

Mixing 2.5D and 3D packaging technologies results in Co-EMIB, which allows larger than grid-sized base punches and Foveros punches on the same package.

Top: The combination of 2.5D and 3D packaging technologies results in Co-EMIB, which provides a larger than grid-sized base punch and Foveros punches on the same package.

However, advanced packaging technologies can not only benefit from higher throughput and lower capacity. The combination of EMIB and Foveros, called Co-EMIB, promises greater scope than either approach. So far, there are no real examples of Co-EMIB. But you can imagine large eco-friendly packages with embedded bridges connecting Fovora chimneys that combine accelerators and memory for high performance.

Intel’s omnidirectional interface (ODI) provides even more flexibility by linking fonts side by side, connecting vertically stacked fonts, and powering the top punch directly through the copper poles. Those poles are larger than the TSVs running through the base, dying in the Fovera stack, reducing resistance and improving power supply. The freedom of the connection dies in any direction and stacking the larger tiles on the smaller ones gives Intel much-needed layout flexibility. This definitely looks like a promising technology to take advantage of Fovera’s potential.


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